duda con programa en VHDL

Iniciado por EdgarKrieger, 16 Octubre 2014, 19:54 PM

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EdgarKrieger

Buenas a todos, tengo una duda con respecto a la programación en VHDL, estoy haciendo un decodificador de hexadecimal a 7 segmentos el código es este:

Código (vhdl) [Seleccionar]
--Decodificar de hexadecimal a 7 segmentos
entity decodificador7 is
port(aa,bb,cc,dd:in bit;
a,b,c,d,e,f,g:out bit);
end decodificador7;

architecture comportamental of decodificador7 is
signal pepe: bit_vector(3 downto 0);
signal sal: bit_vector(6 downto 0);
begin
process
begin
pepe<=aa & bb & cc & dd;
case pepe is
when "0000" => sal <= "0000000";
when "0001" => sal <= "1100000";
when "0010" => sal <= "1011011";
when "0011" => sal <= "1110011";
when "0100" => sal <= "1100101";
when "0101" => sal <= "1011011";
when "0110" => sal <= "0111111";
when "0111" => sal <= "1100010";
when "1000" => sal <= "1111111";
when "1001" => sal <= "1100111";
when "1010" => sal <= "1101111";
when "1011" => sal <= "0111101";
when "1100" => sal <= "0011110";
when "1101" => sal <= "1111001";
when "1110" => sal <= "0011111";
when "1111" => sal <= "0001111";
when others => sal <= "0000000";
end case;
end process;
a<=sal(6);
b<=sal(5);
c<=sal(4);
d<=sal(3);
e<=sal(2);
f<=sal(1);
g<=sal(0);
end comportamental;


pero al momento de compilar me manda el siguiente error:

Código (vhdl) [Seleccionar]

Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
Info: Processing started: Thu Oct 16 12:46:07 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decodificador7 -c decodificador7
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 2 design units, including 1 entities, in source file decodificador7.vhd
Info (12022): Found design unit 1: decodificador7-comportamental
Info (12023): Found entity 1: decodificador7
Info (12127): Elaborating entity "decodificador7" for the top level hierarchy
Error (10442): VHDL Process Statement error at decodificador7.vhd(33): Process Statement must contain either a sensitivity list or a Wait Statement
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 610 megabytes
Error: Processing ended: Thu Oct 16 12:46:08 2014
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings


a que se debe este error :-( :-( y si alguien sabe como puedo corregirlo, muchas gracias por la ayuda  ;D
"Las matemáticas son el lenguaje, el idioma que utilizo Dios para escribir el mundo"
Galileo Galilei